/*---------------------------------------------------------------------------------------------------------*/
/*                                                                                                         */
/* Copyright(c) 2010 Nuvoton Technology Corp. All rights reserved.                                         */
/*                                                                                                         */
/*---------------------------------------------------------------------------------------------------------*/
#ifndef DRVGPIO_H
#define DRVGPIO_H

#include "NANO1xx.h"

/*---------------------------------------------------------------------------------------------------------*/
/*  Define Version number								                                                   */
/*---------------------------------------------------------------------------------------------------------*/
#define DRVGPIO_MAJOR_NUM       1
#define DRVGPIO_MINOR_NUM	    01
#define DRVGPIO_BUILD_NUM	    001

/*---------------------------------------------------------------------------------------------------------*/
/*  Version define with SysInfra				                                                           */
/*---------------------------------------------------------------------------------------------------------*/
#define DRVGPIO_VERSION_NUM     _SYSINFRA_VERSION(DRVGPIO_MAJOR_NUM, DRVGPIO_MINOR_NUM, DRVGPIO_BUILD_NUM)

/*---------------------------------------------------------------------------------------------------------*/
/*  Define Error Code									                                                   */
/*---------------------------------------------------------------------------------------------------------*/
#define E_DRVGPIO_ARGUMENT          _SYSINFRA_ERRCODE(TRUE, MODULE_ID_DRVGPIO, 1)
#define E_DRVGPIO_GROUP_PIN         _SYSINFRA_ERRCODE(TRUE, MODULE_ID_DRVGPIO, 2)
#define E_DRVGPIO_BUSY              _SYSINFRA_ERRCODE(TRUE, MODULE_ID_DRVGPIO, 3)

typedef void (*GPIO_GPABC_CALLBACK)(uint32_t u32GPAStatus, uint32_t u32GPBStatus, uint32_t u32GPCStatus);
typedef void (*GPIO_GPDEF_CALLBACK)(uint32_t u32GPDStatus, uint32_t u32GPEStatus, uint32_t u32GPFStatus);
typedef void (*GPIO_EINT0_CALLBACK)(void);
typedef void (*GPIO_EINT1_CALLBACK)(void);

/* Define GPIO[n] Pin I/O Bit Output Control. */
#define _DRVGPIO_DOUT(PortNum, PinNum)      (*((uint32_t *) ((GPIOBITA_BASE+(0x40*PortNum)) + (0x4*PinNum))))
#define GPA_0	            _DRVGPIO_DOUT(0, 0)
#define GPA_1	            _DRVGPIO_DOUT(0, 1)
#define GPA_2	            _DRVGPIO_DOUT(0, 2)
#define GPA_3	            _DRVGPIO_DOUT(0, 3)
#define GPA_4	            _DRVGPIO_DOUT(0, 4)
#define GPA_5	            _DRVGPIO_DOUT(0, 5)
#define GPA_6	            _DRVGPIO_DOUT(0, 6)
#define GPA_7	            _DRVGPIO_DOUT(0, 7)
#define GPA_8	            _DRVGPIO_DOUT(0, 8)
#define GPA_9	            _DRVGPIO_DOUT(0, 9)
#define GPA_10	            _DRVGPIO_DOUT(0, 10)
#define GPA_11	            _DRVGPIO_DOUT(0, 11)
#define GPA_12	            _DRVGPIO_DOUT(0, 12)
#define GPA_13	            _DRVGPIO_DOUT(0, 13)
#define GPA_14	            _DRVGPIO_DOUT(0, 14)
#define GPA_15	            _DRVGPIO_DOUT(0, 15)
#define GPB_0	            _DRVGPIO_DOUT(1, 0)
#define GPB_1	            _DRVGPIO_DOUT(1, 1)
#define GPB_2	            _DRVGPIO_DOUT(1, 2)
#define GPB_3	            _DRVGPIO_DOUT(1, 3)
#define GPB_4	            _DRVGPIO_DOUT(1, 4)
#define GPB_5	            _DRVGPIO_DOUT(1, 5)
#define GPB_6	            _DRVGPIO_DOUT(1, 6)
#define GPB_7	            _DRVGPIO_DOUT(1, 7)
#define GPB_8	            _DRVGPIO_DOUT(1, 8)
#define GPB_9	            _DRVGPIO_DOUT(1, 9)
#define GPB_10	            _DRVGPIO_DOUT(1, 10)
#define GPB_11	            _DRVGPIO_DOUT(1, 11)
#define GPB_12	            _DRVGPIO_DOUT(1, 12)
#define GPB_13	            _DRVGPIO_DOUT(1, 13)
#define GPB_14	            _DRVGPIO_DOUT(1, 14)
#define GPB_15	            _DRVGPIO_DOUT(1, 15)
#define GPC_0	            _DRVGPIO_DOUT(2, 0)
#define GPC_1	            _DRVGPIO_DOUT(2, 1)
#define GPC_2	            _DRVGPIO_DOUT(2, 2)
#define GPC_3	            _DRVGPIO_DOUT(2, 3)
#define GPC_4	            _DRVGPIO_DOUT(2, 4)
#define GPC_5	            _DRVGPIO_DOUT(2, 5)
#define GPC_6	            _DRVGPIO_DOUT(2, 6)
#define GPC_7	            _DRVGPIO_DOUT(2, 7)
#define GPC_8	            _DRVGPIO_DOUT(2, 8)
#define GPC_9	            _DRVGPIO_DOUT(2, 9)
#define GPC_10	            _DRVGPIO_DOUT(2, 10)
#define GPC_11	            _DRVGPIO_DOUT(2, 11)
#define GPC_12	            _DRVGPIO_DOUT(2, 12)
#define GPC_13	            _DRVGPIO_DOUT(2, 13)
#define GPC_14	            _DRVGPIO_DOUT(2, 14)
#define GPC_15	            _DRVGPIO_DOUT(2, 15)
#define GPD_0	            _DRVGPIO_DOUT(3, 0)
#define GPD_1	            _DRVGPIO_DOUT(3, 1)
#define GPD_2	            _DRVGPIO_DOUT(3, 2)
#define GPD_3	            _DRVGPIO_DOUT(3, 3)
#define GPD_4	            _DRVGPIO_DOUT(3, 4)
#define GPD_5	            _DRVGPIO_DOUT(3, 5)
#define GPD_6	            _DRVGPIO_DOUT(3, 6)
#define GPD_7	            _DRVGPIO_DOUT(3, 7)
#define GPD_8	            _DRVGPIO_DOUT(3, 8)
#define GPD_9	            _DRVGPIO_DOUT(3, 9)
#define GPD_10	            _DRVGPIO_DOUT(3, 10)
#define GPD_11	            _DRVGPIO_DOUT(3, 11)
#define GPD_12	            _DRVGPIO_DOUT(3, 12)
#define GPD_13	            _DRVGPIO_DOUT(3, 13)
#define GPD_14	            _DRVGPIO_DOUT(3, 14)
#define GPD_15	            _DRVGPIO_DOUT(3, 15)
#define GPE_0	            _DRVGPIO_DOUT(4, 0)
#define GPE_1	            _DRVGPIO_DOUT(4, 1)
#define GPE_2	            _DRVGPIO_DOUT(4, 2)
#define GPE_3	            _DRVGPIO_DOUT(4, 3)
#define GPE_4	            _DRVGPIO_DOUT(4, 4)
#define GPE_5	            _DRVGPIO_DOUT(4, 5)
#define GPE_6	            _DRVGPIO_DOUT(4, 6)
#define GPE_7	            _DRVGPIO_DOUT(4, 7)
#define GPE_8	            _DRVGPIO_DOUT(4, 8)
#define GPE_9	            _DRVGPIO_DOUT(4, 9)
#define GPE_10	            _DRVGPIO_DOUT(4, 10)
#define GPE_11	            _DRVGPIO_DOUT(4, 11)
#define GPE_12	            _DRVGPIO_DOUT(4, 12)
#define GPE_13	            _DRVGPIO_DOUT(4, 13)
#define GPE_14	            _DRVGPIO_DOUT(4, 14)
#define GPE_15	            _DRVGPIO_DOUT(4, 15)
#define GPF_0	            _DRVGPIO_DOUT(5, 0)
#define GPF_1	            _DRVGPIO_DOUT(5, 1)
#define GPF_2	            _DRVGPIO_DOUT(5, 2)
#define GPF_3	            _DRVGPIO_DOUT(5, 3)
#define GPF_4	            _DRVGPIO_DOUT(5, 4)
#define GPF_5	            _DRVGPIO_DOUT(5, 5)

/****************************************************/
/* check assert */
#define CHECK_GPIO_PORT(port)	((port==E_GPA)||(port==E_GPB)||(port==E_GPC)||(port==E_GPD)||(port==E_GPE)||(port==E_GPF))
#define CHECK_GPIO_PORTPIN(port, pin)	(((port==E_GPF)&&(pin<6)) || ((port<5)&&(pin<16)))
#define CHECK_GPIO_DEBCYCLE(u32CycleSelection) (u32CycleSelection < 15)
#define CHECK_GPIO_INTTYPE(TriggerType, Mode)	((TriggerType == E_IO_BOTH_EDGE)&&(Mode != E_MODE_LEVEL))

#define CHECK_GPIO_EINT0(port, pin)	((port != E_PORT3) || (pin != 2))
#define CHECK_GPIO_EINT1(port, pin)	((port != E_PORT5) || (pin != 2))


/****************************************************/
typedef enum
{
	E_GPA = 0,
	E_GPB = 1,
	E_GPC = 2,
	E_GPD = 3,
	E_GPE = 4,
	E_GPF = 5
} E_DRVGPIO_PORT;

typedef enum
{
    E_IO_INPUT = 0,
    E_IO_OUTPUT,
    E_IO_OPENDRAIN
} E_DRVGPIO_IO;

typedef enum
{
    E_IO_RISING = 0,
    E_IO_FALLING,
    E_IO_BOTH_EDGE
} E_DRVGPIO_INT_TYPE;

typedef enum
{
    E_MODE_EDGE = 0,
    E_MODE_LEVEL
} E_DRVGPIO_INT_MODE;

typedef enum
{
    E_DBCLKSRC_HCLK = 0,
    E_DBCLKSRC_10K = 1
} E_DRVGPIO_DBCLKSRC;

/*---------------------------------------------------------------------------------------------*/
/*  Define Multi-function pin                                                                  */
/*            Byte3 : [31:24] GCR offset                                                       */
/*            Byte2 : [23:16] shift0                                                           */
/*            Byte1 : [15:8] shift1                                                            */
/*            Byte0 : [7:0] [7:4] value1; [3:0] value0                                         */
/*---------------------------------------------------------------------------------------------*/
typedef enum
{
	E_FUNC_GPIO = 0x0f000000,  E_FUNC_I2S = 0x0f000001,  E_FUNC_SPI0 = 0x0f000002,  E_FUNC_SPI1 = 0x0f000003,
	E_FUNC_SPI2 = 0x0f000004,  E_FUNC_UART0 = 0x0f000005, E_FUNC_UART1 = 0x0f000006,E_FUNC_PWM45 = 0x0f000007,
	E_FUNC_EBI_8B = 0x0f000008,  E_FUNC_EBI_16B = 0x0f000009,

	E_FUNC_CLKO = 0x3C100004,  E_FUNC_I2C0 = 0x34000411,  E_FUNC_I2C1 = 0x34080C11,  E_FUNC_ADC0 = 0x30000001,
	E_FUNC_ADC1 = 0x30040001,  E_FUNC_ADC2 = 0x30080001,  E_FUNC_ADC3 = 0x300C0001,  E_FUNC_ADC4 = 0x30100001,
	E_FUNC_ADC5 = 0x30140001,  E_FUNC_ADC6 = 0x30180001,  E_FUNC_ADC7 = 0x301C0001,  E_FUNC_EXTINT0 = 0x3C180001,
	E_FUNC_EXTINT1 = 0x3C1C0001, E_FUNC_TMR0 = 0x3C000002, E_FUNC_TMR1 = 0x3C040002, E_FUNC_TMR2 = 0x3C080002, 
	E_FUNC_TMR3 = 0x3C0C0002,  E_FUNC_PWM01 = 0x34101411, E_FUNC_PWM23 = 0x34181C11, E_FUNC_PWM67 = 0x50000411 

} E_DRVGPIO_FUNC;

/*---------------------------------------------------------------------------------------------*/
/*  Define External Interrupt pin function data structure                                      */
/*---------------------------------------------------------------------------------------------*/
typedef enum
{
    E_EXT0_GPB8 = 0,
    E_EXT0_GPB9,
    E_EXT0_GPB14,
    E_EXT0_GPC12,
    E_EXT0_GPF0
} E_DRVGPIO_EINT0;

typedef enum
{
    E_EXT1_GPB15 = 0,
    E_EXT1_GPC13,
    E_EXT0_GPF1
} E_DRVGPIO_EINT1;


/*---------------------------------------------------------------------------------------------*/
/*  Define Multi-function pin                                                                  */
/*            Byte3 : [31:24] GCR offset                                                       */
/*            Byte2 : [23:16] shift                                                            */
/*            Byte1 : [15:8] reserved                                                          */
/*            Byte0 : [7:0] value                                                              */
/*---------------------------------------------------------------------------------------------*/

/*---------------------------------------------------------------------------------------------*/
/*  Define RTC Snooper pin function data structure                                             */
/*---------------------------------------------------------------------------------------------*/
typedef enum
{
	E_RTC_GPB15 = 0x3C1CFF03,
	E_RTC_GPC13 = 0x4414FF04
} E_DRVGPIO_RTC;

/*---------------------------------------------------------------------------------------------*/
/*  Define SmartCard 1 pin function data structure                                             */
/*---------------------------------------------------------------------------------------------*/
typedef enum
{
	E_SC1_PORTC,  E_SC1_PORTD
} E_DRVGPIO_SC1;

/*---------------------------------------------------------------------------------------------*/
/*  Define LCD pin function data structure                                                     */
/*---------------------------------------------------------------------------------------------*/
typedef enum
{
	E_LCD_0 = 0x001,    E_LCD_4 = 0x002,    E_LCD_8 = 0x004,    E_LCD_12 = 0x008,
	E_LCD_16 = 0x010,	E_LCD_20 = 0x020,	E_LCD_24 = 0x040,   E_LCD_28 = 0x080,
	E_LCD_32 = 0x100,   E_LCD_36 = 0x200
} E_DRVGPIO_LCDSEG;

typedef enum
{
	E_LCD_100PIN,
	E_LCD_64PIN
} E_DRVGPIO_LCDTYPE;

/*---------------------------------------------------------------------------------------------*/
/*  Define Timer Capture pin function data structure                                           */
/*---------------------------------------------------------------------------------------------*/
typedef enum
{
    E_TC0_GPA12 = 0x3410FF03,   E_TC0_GPC6 = 0x4018FF03,    E_TC0_GPC15 = 0x441CFF03,
    E_TC1_GPA13 = 0x3414FF03,   E_TC1_GPC7 = 0x401CFF03,
    E_TC2_GPA7 = 0x301CFF03,    E_TC2_GPA14 = 0x3418FF03,
    E_TC3_GPA6 = 0x3018FF03,    E_TC3_GPA15 = 0x341CFF03
} E_DRVGPIO_TMRCAP;

/*---------------------------------------------------------------------------------------------*/
/*  Define PWM pin function data structure                                                     */
/*---------------------------------------------------------------------------------------------*/
typedef enum
{
    E_PWM0_CH0_GPA12 = 0x3410FF01,   E_PWM0_CH0_GPC6 = 0x4018FF05,
    E_PWM0_CH1_GPA13 = 0x3414FF01,   E_PWM0_CH1_GPC7 = 0x401CFF05,
    E_PWM0_CH2_GPA7 = 0x301CFF05,    E_PWM0_CH2_GPA14 = 0x3418FF01,
    E_PWM0_CH3_GPA6 = 0x3018FF05,    E_PWM0_CH3_GPA15 = 0x341CFF01,

    E_PWM1_CH0_GPB11 = 0x3C0CFF01,   E_PWM1_CH0_GPC12 = 0x4410FF02,
    E_PWM1_CH1_GPC13 = 0x4414FF02,   E_PWM1_CH1_GPE5 = 0x5014FF01,
    E_PWM1_CH2_GPC15 = 0x441CFF04,   E_PWM1_CH2_GPE0 = 0x5000FF01,
    E_PWM1_CH3_GPC14 = 0x4418FF04,   E_PWM1_CH3_GPE1 = 0x5004FF01
} E_DRVGPIO_PWM;

/*---------------------------------------------------------------------------------------------*/
/*  Define I2S pin function data structure                                                     */
/*---------------------------------------------------------------------------------------------*/
typedef enum
{
    E_I2S_MCLK_GPA15 = 0x341CFF02,   E_I2S_MCLK_GPE0 = 0x5000FF02
} E_DRVGPIO_I2S_MCLK;

typedef enum
{
    E_I2S_WS_GPC0 = 0x4000FF02,   E_I2S_WS_GPD2 = 0x4808FF02
} E_DRVGPIO_I2S_WS;

typedef enum
{
    E_I2S_BCLK_GPC1 = 0x4004FF02,   E_I2S_BCLK_GPD3 = 0x480CFF02
} E_DRVGPIO_I2S_BCLK;

typedef enum
{
    E_I2S_DIN_GPC2 = 0x4008FF02,   E_I2S_DIN_GPD4 = 0x4810FF02
} E_DRVGPIO_I2S_DIN;

typedef enum
{
    E_I2S_DOUT_GPC3 = 0x400CFF02,   E_I2S_DOUT_GPD5 = 0x4814FF02
} E_DRVGPIO_I2S_DOUT;

typedef struct DRVGPIO_I2S_STRUCT
{
	E_DRVGPIO_I2S_MCLK	mclk;
	E_DRVGPIO_I2S_WS	ws_out;
	E_DRVGPIO_I2S_BCLK	bclk;
	E_DRVGPIO_I2S_DIN	din;
	E_DRVGPIO_I2S_DOUT	dout;
}STR_GPIO_I2S_T;

/*---------------------------------------------------------------------------------------------------------*/
/*  Define I2C pin function data structure                                                                 */
/*---------------------------------------------------------------------------------------------------------*/
typedef enum
{
    E_I2C0_SDA_GPA4 = 0x3010FF05,   E_I2C0_SDA_GPA8 = 0x3400FF01,   E_I2C0_SDA_GPA12 = 0x3410FF05,
    E_I2C0_SDA_GPC12 = 0x4410FF06,  E_I2C0_SDA_GPF4 = 0x5810FF01,   E_I2C0_SDA_NONE = 0
} E_DRVGPIO_I2C0_SDA;

typedef enum
{
    E_I2C0_SCK_GPA5 = 0x3014FF05,   E_I2C0_SCK_GPA9 = 0x3404FF01,   E_I2C0_SCK_GPA13 = 0x3414FF05,
    E_I2C0_SCK_GPC13 = 0x4414FF06,  E_I2C0_SCK_GPF5 = 0x5814FF01,   E_I2C0_SCK_NONE = 0
} E_DRVGPIO_I2C0_SCK;

typedef enum
{
    E_I2C1_SDA_GPA10 = 0x3408FF01,  E_I2C1_SDA_GPC8 = 0x4400FF05,   E_I2C1_SDA_NONE = 0
} E_DRVGPIO_I2C1_SDA;

typedef enum
{
    E_I2C1_SCK_GPA11 = 0x340CFF01,  E_I2C1_SCK_GPC9 = 0x4404FF05,   E_I2C1_SCK_NONE = 0
} E_DRVGPIO_I2C1_SCK;

typedef struct DRVGPIO_I2C0_STRUCT
{
	E_DRVGPIO_I2C0_SDA	i2c0SDA;
	E_DRVGPIO_I2C0_SCK	i2c0SCK;
}STR_GPIO_I2C0_T;

typedef struct DRVGPIO_I2C1_STRUCT
{
	E_DRVGPIO_I2C1_SDA	i2c1SDA;
	E_DRVGPIO_I2C1_SCK	i2c1SCK;
}STR_GPIO_I2C1_T;

/*---------------------------------------------------------------------------------------------------------*/
/*  Define SPI0 pin function data structure                                                                */
/*---------------------------------------------------------------------------------------------------------*/
typedef enum
{
    E_SPI0_CLK_GPC1 = 0x4004FF01,   E_SPI0_CLK_GPE2 = 0x5008FF06
} E_DRVGPIO_SPI0_CLK;

typedef enum
{
    E_SPI0_SS0_GPC0 = 0x4000FF01,   E_SPI0_SS0_GPE1 = 0x5004FF06,   E_SPI0_SS0_NONE = 0
} E_DRVGPIO_SPI0_SS0;

typedef enum
{
    E_SPI0_MISO0_GPB11 = 0x3C0CFF05,   E_SPI0_MISO0_GPC2 = 0x4008FF01,   E_SPI0_MISO0_GPE3 = 0x500CFF06
} E_DRVGPIO_SPI0_MISO0;

typedef enum
{
    E_SPI0_MOSI0_GPB10 = 0x3C08FF05,   E_SPI0_MOSI0_GPC3 = 0x400CFF01,   E_SPI0_MOSI0_GPE4 = 0x5010FF06
} E_DRVGPIO_SPI0_MOSI0;

typedef struct DRVGPIO_SPI0_STRUCT
{
	E_DRVGPIO_SPI0_CLK		clk;
	E_DRVGPIO_SPI0_SS0		ss0;
	uint8_t					ss1;	/* 1 is ON (select GPB10); 0 is OFF (do NOT use it pin) */
	E_DRVGPIO_SPI0_MISO0	miso0;
	E_DRVGPIO_SPI0_MOSI0	mosi0;
	uint8_t					miso1;	/* 1 is ON (select GPC4); 0 is OFF (do NOT use it pin) */
	uint8_t					mosi1;	/* 1 is ON (select GPC5); 0 is OFF (do NOT use it pin) */
}STR_GPIO_SPI0_T;

/*---------------------------------------------------------------------------------------------------------*/
/*  Define SPI1 pin function data structure                                                                */
/*---------------------------------------------------------------------------------------------------------*/
typedef enum
{
    E_SPI1_CLK_GPB2 = 0x3808FF03,   E_SPI1_CLK_GPC9 = 0x4404FF01
} E_DRVGPIO_SPI1_CLK;

typedef enum
{
    E_SPI1_SS0_GPB3 = 0x380CFF03,   E_SPI1_SS0_GPC8 = 0x4400FF01,   E_SPI1_SS0_NONE = 0
} E_DRVGPIO_SPI1_SS0;

typedef enum
{
    E_SPI1_MISO0_GPB1 = 0x3804FF03,   E_SPI1_MISO0_GPC10 = 0x4408FF01
} E_DRVGPIO_SPI1_MISO0;

typedef enum
{
    E_SPI1_MOSI0_GPB0 = 0x3800FF03,   E_SPI1_MOSI0_GPC11 = 0x440CFF01
} E_DRVGPIO_SPI1_MOSI0;

typedef struct DRVGPIO_SPI1_STRUCT
{
	E_DRVGPIO_SPI1_CLK		clk;
	E_DRVGPIO_SPI1_SS0		ss0;
	uint8_t					ss1;	/* 1 is ON (select GPB9); 0 is OFF (do NOT use it pin) */
	E_DRVGPIO_SPI1_MISO0	miso0;
	E_DRVGPIO_SPI1_MOSI0	mosi0;
	uint8_t					miso1;	/* 1 is ON (select GPC12); 0 is OFF (do NOT use it pin) */
	uint8_t					mosi1;	/* 1 is ON (select GPC13); 0 is OFF (do NOT use it pin) */
}STR_GPIO_SPI1_T;

/*---------------------------------------------------------------------------------------------------------*/
/*  Define SPI2 pin function data structure                                                                */
/*---------------------------------------------------------------------------------------------------------*/
typedef enum
{
    E_SPI2_CLK_GPA9 = 0x3404FF04,   E_SPI2_CLK_GPB5 = 0x3814FF04,   E_SPI2_CLK_GPD1 = 0x4804FF03
} E_DRVGPIO_SPI2_CLK;

typedef enum
{
    E_SPI2_SS0_GPA8 = 0x3400FF04,   E_SPI2_SS0_GPB4 = 0x3810FF04,   E_SPI2_SS0_GPD0 = 0x4800FF03,   E_SPI2_SS0_NONE = 0
} E_DRVGPIO_SPI2_SS0;

typedef enum
{
    E_SPI2_MISO0_GPA10 = 0x3408FF04,   E_SPI2_MISO0_GPB6 = 0x3818FF04,   E_SPI2_MISO0_GPD2 = 0x4808FF03
} E_DRVGPIO_SPI2_MISO0;

typedef enum
{
    E_SPI2_MOSI0_GPA11 = 0x340CFF04,   E_SPI2_MOSI0_GPB7 = 0x381CFF04,   E_SPI2_MOSI0_GPD3 = 0x480CFF03
} E_DRVGPIO_SPI2_MOSI0;

typedef struct DRVGPIO_SPI2_STRUCT
{
	E_DRVGPIO_SPI2_CLK		clk;
	E_DRVGPIO_SPI2_SS0		ss0;
	uint8_t					ss1;	/* 1 is ON (select GPB14); 0 is OFF (do NOT use it pin) */
	E_DRVGPIO_SPI2_MISO0	miso0;
	E_DRVGPIO_SPI2_MOSI0	mosi0;
	uint8_t					miso1;	/* 1 is ON (select GPD4); 0 is OFF (do NOT use it pin) */
	uint8_t					mosi1;	/* 1 is ON (select GPD5); 0 is OFF (do NOT use it pin) */
}STR_GPIO_SPI2_T;

/*---------------------------------------------------------------------------------------------------------*/
/*  Define UART0 pin function data structure                                                               */
/*---------------------------------------------------------------------------------------------------------*/
typedef enum
{
    E_UART0_RX_GPA14 = 0x3418FF06,   E_UART0_RX_GPB0 = 0x3800FF01,   E_UART0_RX_NONE = 0
} E_DRVGPIO_UART0_RX;

typedef enum
{
    E_UART0_TX_GPA15 = 0x341CFF06,   E_UART0_TX_GPB1 = 0x3804FF01,   E_UART0_TX_NONE = 0
} E_DRVGPIO_UART0_TX;

typedef enum
{
    E_UART0_RTS_GPB2 = 0x3808FF01,   E_UART0_RTS_NONE = 0
} E_DRVGPIO_UART0_RTS;

typedef enum
{
    E_UART0_CTS_GPB3 = 0x380CFF01,   E_UART0_CTS_NONE = 0
} E_DRVGPIO_UART0_CTS;

typedef struct DRVGPIO_UART0_STRUCT
{
	E_DRVGPIO_UART0_RX		rx;
	E_DRVGPIO_UART0_TX		tx;
	E_DRVGPIO_UART0_RTS		rts;
	E_DRVGPIO_UART0_CTS		cts;
}STR_GPIO_UART0_T;

/*---------------------------------------------------------------------------------------------------------*/
/*  Define UART1 pin function data structure                                                               */
/*---------------------------------------------------------------------------------------------------------*/
typedef enum
{
    E_UART1_RX_GPA2 = 0x3008FF05,   E_UART1_RX_GPB4 = 0x3810FF01,   E_UART1_RX_GPC10 = 0x4408FF05,
    E_UART1_RX_GPD0 = 0x4800FF01,   E_UART1_RX_GPE9 = 0x5404FF07,   E_UART1_RX_NONE = 0
} E_DRVGPIO_UART1_RX;

typedef enum
{
    E_UART1_TX_GPA3 = 0x300CFF05,   E_UART1_TX_GPB5 = 0x3814FF01,   E_UART1_TX_GPC11 = 0x440CFF05,
    E_UART1_TX_GPD1 = 0x4804FF01,   E_UART1_TX_GPE10 = 0x5408FF07,  E_UART1_TX_NONE = 0
} E_DRVGPIO_UART1_TX;

typedef enum
{
    E_UART1_RTS_GPB6 = 0x3810FF01,   E_UART1_RTS_GPD2 = 0x4808FF01,   E_UART1_RTS_GPE11 = 0x540CFF07,
    E_UART1_RTS_NONE = 0
} E_DRVGPIO_UART1_RTS;

typedef enum
{
    E_UART1_CTS_GPB7 = 0x3810FF01,   E_UART1_CTS_GPD3 = 0x480CFF01,   E_UART1_CTS_GPE12 = 0x5410FF07,
    E_UART1_CTS_NONE = 0
} E_DRVGPIO_UART1_CTS;

typedef struct DRVGPIO_UART1_STRUCT
{
	E_DRVGPIO_UART1_RX		rx;
	E_DRVGPIO_UART1_TX		tx;
	E_DRVGPIO_UART1_RTS		rts;
	E_DRVGPIO_UART1_CTS		cts;
}STR_GPIO_UART1_T;


/*---------------------------------------------------------------------------------------------*/
/*  Define Multi-function pin                                                                  */
/*            Byte3 : [31:24] GCR offset                                                       */
/*            Byte2 : [23:16] shift0                                                           */
/*            Byte1 : [15:8] shift1                                                            */
/*            Byte0 : [7:0] [7:4] value1; [3:0] value0                                         */
/*---------------------------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------------------------*/
/*  Define DAC pin function data structure                                                     */
/*---------------------------------------------------------------------------------------------*/
typedef enum
{
	E_DAC_OUT0 = 0x40180001,   E_DAC_OUT1 = 0x401C0001,   E_DAC_ALL = 0x40181C11
} E_DRVGPIO_DAC;


/*---------------------------------------------------------------------------------------------------------*/
/* Define GPIO functions prototype                                                                         */
/*---------------------------------------------------------------------------------------------------------*/
int32_t DrvGPIO_Open(E_DRVGPIO_PORT port, int32_t i32Bit, E_DRVGPIO_IO mode);
int32_t DrvGPIO_Close(E_DRVGPIO_PORT port, int32_t i32Bit);
int32_t DrvGPIO_SetBit(E_DRVGPIO_PORT port, int32_t i32Bit);
int32_t DrvGPIO_GetBit(E_DRVGPIO_PORT port, int32_t i32Bit);
int32_t DrvGPIO_ClrBit(E_DRVGPIO_PORT port, int32_t i32Bit);
int32_t DrvGPIO_SetPortBits(E_DRVGPIO_PORT port, int32_t i32Data);
int32_t DrvGPIO_GetPortBits(E_DRVGPIO_PORT port);
int32_t DrvGPIO_GetDoutBit(E_DRVGPIO_PORT port, int32_t i32Bit);
int32_t DrvGPIO_GetPortDoutBits(E_DRVGPIO_PORT port);
int32_t DrvGPIO_SetBitMask(E_DRVGPIO_PORT port, int32_t i32Bit);
int32_t DrvGPIO_GetBitMask(E_DRVGPIO_PORT port, int32_t i32Bit);
int32_t DrvGPIO_ClrBitMask(E_DRVGPIO_PORT port, int32_t i32Bit);
int32_t DrvGPIO_SetPortMask(E_DRVGPIO_PORT port, int32_t i32MaskData);
int32_t DrvGPIO_GetPortMask(E_DRVGPIO_PORT port);
int32_t DrvGPIO_ClrPortMask(E_DRVGPIO_PORT port, int32_t i32MaskData);
int32_t DrvGPIO_EnablePullup(E_DRVGPIO_PORT port, int32_t i32Bit);
int32_t DrvGPIO_DisablePullup(E_DRVGPIO_PORT port, int32_t i32Bit);
int32_t DrvGPIO_EnableDebounce(E_DRVGPIO_PORT port, int32_t i32Bit);
int32_t DrvGPIO_DisableDebounce(E_DRVGPIO_PORT port, int32_t i32Bit);
int32_t DrvGPIO_SetDebounceTime(uint32_t u32CycleSelection, E_DRVGPIO_DBCLKSRC ClockSource);
int32_t DrvGPIO_GetDebounceSampleCycle(void);
int32_t DrvGPIO_EnableInt(E_DRVGPIO_PORT port, int32_t i32Bit, E_DRVGPIO_INT_TYPE TriggerType, E_DRVGPIO_INT_MODE Mode);
int32_t DrvGPIO_DisableInt(E_DRVGPIO_PORT port, int32_t i32Bit);
void DrvGPIO_SetIntCallback(GPIO_GPABC_CALLBACK pfGPABCCallback, GPIO_GPDEF_CALLBACK pfGPDEFCallback);
void DrvGPIO_EnableEINT0(E_DRVGPIO_INT_TYPE TriggerType, E_DRVGPIO_INT_MODE Mode, GPIO_EINT0_CALLBACK pfEINT0Callback);
void DrvGPIO_EnableEINT0_Ex(E_DRVGPIO_INT_TYPE TriggerType, E_DRVGPIO_INT_MODE Mode,
							GPIO_EINT0_CALLBACK pfEINT0Callback, E_DRVGPIO_EINT0 Ext0);
void DrvGPIO_DisableEINT0(void);
void DrvGPIO_EnableEINT1(E_DRVGPIO_INT_TYPE TriggerType, E_DRVGPIO_INT_MODE Mode, GPIO_EINT1_CALLBACK pfEINT1Callback);
void DrvGPIO_EnableEINT1_Ex(E_DRVGPIO_INT_TYPE TriggerType, E_DRVGPIO_INT_MODE Mode,
							GPIO_EINT1_CALLBACK pfEINT1Callback, E_DRVGPIO_EINT1 Ext1);
void DrvGPIO_DisableEINT1(void);
int32_t DrvGPIO_GetIntStatus(E_DRVGPIO_PORT port);
int32_t DrvGPIO_InitFunction(E_DRVGPIO_FUNC function);
int32_t DrvGPIO_GetVersion(void);

int32_t DrvGPIO_InitRTCSnooper(E_DRVGPIO_RTC pin);
int32_t DrvGPIO_InitSmartCard0(void);
int32_t DrvGPIO_InitSmartCard1(E_DRVGPIO_SC1 port);
int32_t DrvGPIO_InitLCD(E_DRVGPIO_LCDTYPE type, E_DRVGPIO_LCDSEG seg);
int32_t DrvGPIO_InitTouchKey(uint32_t cap, uint16_t KeyMask);
int32_t DrvGPIO_InitTimerCapture(E_DRVGPIO_TMRCAP tcNo);
int32_t DrvGPIO_InitPWM(E_DRVGPIO_PWM channel);
int32_t DrvGPIO_InitI2S(STR_GPIO_I2S_T *I2SFun);
int32_t DrvGPIO_InitI2C0(STR_GPIO_I2C0_T *I2CFun);
int32_t DrvGPIO_InitI2C1(STR_GPIO_I2C1_T *I2CFun);
int32_t DrvGPIO_InitSPI0(STR_GPIO_SPI0_T *SPIFun);
int32_t DrvGPIO_InitSPI1(STR_GPIO_SPI1_T *SPIFun);
int32_t DrvGPIO_InitSPI2(STR_GPIO_SPI2_T *SPIFun);
int32_t DrvGPIO_InitUART0(STR_GPIO_UART0_T *uartFun);
int32_t DrvGPIO_InitUART1(STR_GPIO_UART1_T *uartFun);
int32_t DrvGPIO_InitDAC(E_DRVGPIO_DAC function);
int32_t DrvGPIO_InitGPIO(E_DRVGPIO_PORT port, int32_t i32Bit);


#endif








